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dev-cpp/xsimd: add 13.0.0, including backports needed by media-gfx/krita
See https://mail.kde.org/pipermail/distributions/2024-July/001511.html. Signed-off-by: Sam James <sam@gentoo.org>
This commit is contained in:
Sam James
@@ -1,2 +1,3 @@
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DIST xsimd-11.1.0.tar.gz 219350 BLAKE2B 2bbbc4f7dbe489a407fe798b146c008aba44664efc943c2e1507d5c6e7da2a03ed91abf0d872e5abf9bd94be3e76bef276ec5b47d4e356b42a7b4c680bd6f3d9 SHA512 3a6141dfa4d95a977f4222880dfd06197613d153a78a84653022423279eec037ea9def08ae225aba7231c0b2c434ab7c907c965f8367fb0db9b96113980b51f3
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DIST xsimd-12.1.1.tar.gz 253141 BLAKE2B 29efbb045d8ade8737d702a73f3d0a912111dd4fbc84485c0e54c8b06d73edbb4b85f4b51e24da9bed0dea010b0cce9d99b57e20e8b94d3daf90d46031548eb9 SHA512 8e45a8e9b28358d5f20f713ea19a8c366edc62790c27984149f283dfe808d78a549c8ec465e8b3677d7e30b2cb80093908de364bbb9dc80683f5fdfb843131e1
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DIST xsimd-13.0.0.tar.gz 259967 BLAKE2B 63267c75a7e8ed2e8689a912e79a1d012ff3cf3813969f97a640801e372ec9e66a6e3d3034b6918a30dc3374e8211fd1107f1309156354b6bca6ba17c6f132b4 SHA512 cdc42ddad3353297cf25ea2b6b3f09967f5f388efc26241f2997979fdbbac072819ff771145bc5bfa86cb326cca84b4119e8e6e3f658407961cf203a40603a7f
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@@ -0,0 +1,148 @@
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https://mail.kde.org/pipermail/distributions/2024-July/001511.html
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https://github.com/xtensor-stack/xsimd/commit/96edf0340492fa9c080f5182b38358ca85baef5e
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From 96edf0340492fa9c080f5182b38358ca85baef5e Mon Sep 17 00:00:00 2001
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From: Dmitry Kazakov <dimula73@gmail.com>
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Date: Tue, 28 May 2024 22:21:08 +0200
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Subject: [PATCH] Fix detection of SSE/AVX/AVX512 when they are explicitly
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disabled by OS
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Some CPU vulnerability mitigations may disable AVX functionality
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on the hardware level via the XCR0 register. We should check that
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manually to verify that OS actually allows us to use this feature.
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See https://bugs.kde.org/show_bug.cgi?id=484622
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Fix #1025
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---
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include/xsimd/config/xsimd_cpuid.hpp | 91 ++++++++++++++++++++++------
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1 file changed, 72 insertions(+), 19 deletions(-)
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diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
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index f22089bac..6dda3be09 100644
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--- a/include/xsimd/config/xsimd_cpuid.hpp
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+++ b/include/xsimd/config/xsimd_cpuid.hpp
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@@ -114,6 +114,35 @@ namespace xsimd
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#endif
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#elif defined(__x86_64__) || defined(__i386__) || defined(_M_AMD64) || defined(_M_IX86)
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+
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+ auto get_xcr0_low = []() noexcept
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+ {
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+ uint32_t xcr0;
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+
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+#if defined(_MSC_VER) && _MSC_VER >= 1400
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+
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+ xcr0 = (uint32_t)_xgetbv(0);
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+
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+#elif defined(__GNUC__)
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+
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+ __asm__(
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+ "xorl %%ecx, %%ecx\n"
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+ "xgetbv\n"
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+ : "=a"(xcr0)
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+ :
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+#if defined(__i386__)
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+ : "ecx", "edx"
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+#else
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+ : "rcx", "rdx"
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+#endif
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+ );
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+
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+#else /* _MSC_VER < 1400 */
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+#error "_MSC_VER < 1400 is not supported"
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+#endif /* _MSC_VER && _MSC_VER >= 1400 */
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+ return xcr0;
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+ };
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+
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auto get_cpuid = [](int reg[4], int level, int count = 0) noexcept
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{
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@@ -148,19 +177,43 @@ namespace xsimd
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get_cpuid(regs1, 0x1);
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- sse2 = regs1[3] >> 26 & 1;
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- sse3 = regs1[2] >> 0 & 1;
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- ssse3 = regs1[2] >> 9 & 1;
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- sse4_1 = regs1[2] >> 19 & 1;
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- sse4_2 = regs1[2] >> 20 & 1;
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- fma3_sse42 = regs1[2] >> 12 & 1;
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+ // OS can explicitly disable the usage of SSE/AVX extensions
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+ // by setting an appropriate flag in CR0 register
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+ //
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+ // https://docs.kernel.org/admin-guide/hw-vuln/gather_data_sampling.html
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+
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+ unsigned sse_state_os_enabled = 1;
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+ unsigned avx_state_os_enabled = 1;
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+ unsigned avx512_state_os_enabled = 1;
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+
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+ // OSXSAVE: A value of 1 indicates that the OS has set CR4.OSXSAVE[bit
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+ // 18] to enable XSETBV/XGETBV instructions to access XCR0 and
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+ // to support processor extended state management using
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+ // XSAVE/XRSTOR.
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+ bool osxsave = regs1[2] >> 27 & 1;
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+ if (osxsave)
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+ {
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+
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+ uint32_t xcr0 = get_xcr0_low();
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+
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+ sse_state_os_enabled = xcr0 >> 1 & 1;
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+ avx_state_os_enabled = xcr0 >> 2 & sse_state_os_enabled;
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+ avx512_state_os_enabled = xcr0 >> 6 & avx_state_os_enabled;
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+ }
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+
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+ sse2 = regs1[3] >> 26 & sse_state_os_enabled;
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+ sse3 = regs1[2] >> 0 & sse_state_os_enabled;
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+ ssse3 = regs1[2] >> 9 & sse_state_os_enabled;
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+ sse4_1 = regs1[2] >> 19 & sse_state_os_enabled;
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+ sse4_2 = regs1[2] >> 20 & sse_state_os_enabled;
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+ fma3_sse42 = regs1[2] >> 12 & sse_state_os_enabled;
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- avx = regs1[2] >> 28 & 1;
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+ avx = regs1[2] >> 28 & avx_state_os_enabled;
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fma3_avx = avx && fma3_sse42;
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int regs8[4];
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get_cpuid(regs8, 0x80000001);
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- fma4 = regs8[2] >> 16 & 1;
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+ fma4 = regs8[2] >> 16 & avx_state_os_enabled;
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// sse4a = regs[2] >> 6 & 1;
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@@ -168,23 +221,23 @@ namespace xsimd
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int regs7[4];
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get_cpuid(regs7, 0x7);
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- avx2 = regs7[1] >> 5 & 1;
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+ avx2 = regs7[1] >> 5 & avx_state_os_enabled;
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int regs7a[4];
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get_cpuid(regs7a, 0x7, 0x1);
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- avxvnni = regs7a[0] >> 4 & 1;
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+ avxvnni = regs7a[0] >> 4 & avx_state_os_enabled;
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fma3_avx2 = avx2 && fma3_sse42;
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- avx512f = regs7[1] >> 16 & 1;
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- avx512cd = regs7[1] >> 28 & 1;
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- avx512dq = regs7[1] >> 17 & 1;
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- avx512bw = regs7[1] >> 30 & 1;
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- avx512er = regs7[1] >> 27 & 1;
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- avx512pf = regs7[1] >> 26 & 1;
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- avx512ifma = regs7[1] >> 21 & 1;
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- avx512vbmi = regs7[2] >> 1 & 1;
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- avx512vnni_bw = regs7[2] >> 11 & 1;
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+ avx512f = regs7[1] >> 16 & avx512_state_os_enabled;
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+ avx512cd = regs7[1] >> 28 & avx512_state_os_enabled;
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+ avx512dq = regs7[1] >> 17 & avx512_state_os_enabled;
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+ avx512bw = regs7[1] >> 30 & avx512_state_os_enabled;
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+ avx512er = regs7[1] >> 27 & avx512_state_os_enabled;
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+ avx512pf = regs7[1] >> 26 & avx512_state_os_enabled;
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+ avx512ifma = regs7[1] >> 21 & avx512_state_os_enabled;
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+ avx512vbmi = regs7[2] >> 1 & avx512_state_os_enabled;
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+ avx512vnni_bw = regs7[2] >> 11 & avx512_state_os_enabled;
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avx512vnni_vbmi = avx512vbmi && avx512vnni_bw;
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#endif
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}
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88
dev-cpp/xsimd/files/xsimd-13.0.0-sve-rvv.patch
Normal file
88
dev-cpp/xsimd/files/xsimd-13.0.0-sve-rvv.patch
Normal file
@@ -0,0 +1,88 @@
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https://mail.kde.org/pipermail/distributions/2024-July/001511.html
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https://github.com/xtensor-stack/xsimd/commit/80a59235e3ffa51659aaa06f002bfd088b77023c
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From 80a59235e3ffa51659aaa06f002bfd088b77023c Mon Sep 17 00:00:00 2001
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From: Dmitry Kazakov <dimula73@gmail.com>
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Date: Fri, 14 Jun 2024 10:19:55 +0200
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Subject: [PATCH] Fix xsimd::available_architectures().has() for sve and rvv
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archs
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Ideally the patch CPU detection code should also check if the length
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of SVE and RVV is actually supported by the current CPU implementation
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(i.e. ZCR_Elx.LEN register for SVE and something else for RVV), but
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I don't have such CPUs/emulators handy, so I cannot add such checks.
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Given that xsimd::available_architectures().has() is a new feature
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of XSIMD13 and the length check has never been present in XSIMD, this
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bug is not a regression at least.
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The patch also adds a unittest that reproduces the error the patch fixes
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---
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include/xsimd/config/xsimd_cpuid.hpp | 12 ++++++++++--
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test/test_arch.cpp | 15 +++++++++++++++
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2 files changed, 25 insertions(+), 2 deletions(-)
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diff --git a/include/xsimd/config/xsimd_cpuid.hpp b/include/xsimd/config/xsimd_cpuid.hpp
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index 6dda3be09..8021fceb8 100644
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--- a/include/xsimd/config/xsimd_cpuid.hpp
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+++ b/include/xsimd/config/xsimd_cpuid.hpp
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@@ -42,6 +42,10 @@ namespace xsimd
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#define ARCH_FIELD_EX(arch, field_name) \
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unsigned field_name; \
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XSIMD_INLINE bool has(::xsimd::arch) const { return this->field_name; }
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+
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+#define ARCH_FIELD_EX_REUSE(arch, field_name) \
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+ XSIMD_INLINE bool has(::xsimd::arch) const { return this->field_name; }
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+
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#define ARCH_FIELD(name) ARCH_FIELD_EX(name, name)
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ARCH_FIELD(sse2)
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@@ -72,8 +76,12 @@ namespace xsimd
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ARCH_FIELD(neon)
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ARCH_FIELD(neon64)
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ARCH_FIELD_EX(i8mm<::xsimd::neon64>, i8mm_neon64)
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- ARCH_FIELD(sve)
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- ARCH_FIELD(rvv)
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+ ARCH_FIELD_EX(detail::sve<512>, sve)
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+ ARCH_FIELD_EX_REUSE(detail::sve<256>, sve)
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+ ARCH_FIELD_EX_REUSE(detail::sve<128>, sve)
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+ ARCH_FIELD_EX(detail::rvv<512>, rvv)
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+ ARCH_FIELD_EX_REUSE(detail::rvv<256>, rvv)
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+ ARCH_FIELD_EX_REUSE(detail::rvv<128>, rvv)
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ARCH_FIELD(wasm)
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#undef ARCH_FIELD
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diff --git a/test/test_arch.cpp b/test/test_arch.cpp
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index b42073358..f1f50d546 100644
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--- a/test/test_arch.cpp
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+++ b/test/test_arch.cpp
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@@ -38,6 +38,16 @@ struct check_supported
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}
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};
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+struct check_cpu_has_intruction_set
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+{
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+ template <class Arch>
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+ void operator()(Arch arch) const
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+ {
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+ static_assert(std::is_same<decltype(xsimd::available_architectures().has(arch)), bool>::value,
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+ "cannot test instruction set availability on CPU");
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+ }
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+};
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+
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struct check_available
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{
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template <class Arch>
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@@ -71,6 +81,11 @@ TEST_CASE("[multi arch support]")
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xsimd::supported_architectures::for_each(check_supported {});
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}
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+ SUBCASE("xsimd::available_architectures::has")
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+ {
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+ xsimd::all_architectures::for_each(check_cpu_has_intruction_set {});
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+ }
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+
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SUBCASE("xsimd::default_arch::name")
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{
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constexpr char const* name = xsimd::default_arch::name();
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60
dev-cpp/xsimd/xsimd-13.0.0.ebuild
Normal file
60
dev-cpp/xsimd/xsimd-13.0.0.ebuild
Normal file
@@ -0,0 +1,60 @@
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# Copyright 2023-2024 Gentoo Authors
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# Distributed under the terms of the GNU General Public License v2
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EAPI=8
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inherit cmake
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DESCRIPTION="C++ wrappers for SIMD intrinsics"
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HOMEPAGE="https://github.com/xtensor-stack/xsimd"
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SRC_URI="https://github.com/xtensor-stack/${PN}/archive/refs/tags/${PV}.tar.gz
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-> ${P}.tar.gz"
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LICENSE="BSD"
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SLOT="0"
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KEYWORDS="~amd64 ~arm ~arm64 ~hppa ~loong ~ppc ~ppc64 ~riscv ~s390 ~sparc ~x86"
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IUSE="doc test"
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RESTRICT="!test? ( test )"
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BDEPEND="
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doc? (
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app-text/doxygen
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dev-python/breathe
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dev-python/sphinx
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dev-python/sphinx-rtd-theme
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)
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test? ( dev-cpp/doctest )"
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PATCHES=(
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"${FILESDIR}"/${PN}-11.1.0-c++17.patch
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"${FILESDIR}"/${PN}-12.1.1-no-march.patch
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"${FILESDIR}"/${PN}-13.0.0-sve-rvv.patch
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"${FILESDIR}"/${PN}-13.0.0-detection-simd-with-mitigations.patch
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)
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src_prepare() {
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sed -i \
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-e '/fPIC/d' \
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test/CMakeLists.txt \
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|| die
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cmake_src_prepare
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}
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src_configure() {
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local mycmakeargs=(
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-DBUILD_TESTS=$(usex test)
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)
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cmake_src_configure
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}
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src_compile() {
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cmake_src_compile
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use doc && emake -C docs html
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}
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src_install() {
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cmake_src_install
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if use doc; then
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dodoc -r docs/build/html
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fi
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}
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Reference in New Issue
Block a user