diff --git a/dev-ml/core_unix/core_unix-0.17.1.ebuild b/dev-ml/core_unix/core_unix-0.17.1.ebuild
index 5cf57a86ca537..4ba27b43d1470 100644
--- a/dev-ml/core_unix/core_unix-0.17.1.ebuild
+++ b/dev-ml/core_unix/core_unix-0.17.1.ebuild
@@ -34,6 +34,7 @@ BDEPEND=">=dev-ml/dune-3.11"
 
 PATCHES=(
 	"${FILESDIR}"/${PN}-0.17.0-musl.patch
+	"${FILESDIR}"/${P}-riscv.patch
 )
 
 src_prepare() {
diff --git a/dev-ml/core_unix/files/core_unix-0.17.1-riscv.patch b/dev-ml/core_unix/files/core_unix-0.17.1-riscv.patch
new file mode 100644
index 0000000000000..f59541153de5e
--- /dev/null
+++ b/dev-ml/core_unix/files/core_unix-0.17.1-riscv.patch
@@ -0,0 +1,16 @@
+--- a/time_stamp_counter/src/time_stamp_counter_stubs.c	2025-07-12 22:31:10.112736714 +0200
++++ b/time_stamp_counter/src/time_stamp_counter_stubs.c	2025-07-12 22:34:08.599793338 +0200
+@@ -44,6 +44,13 @@
+   asm volatile("mrs %0, cntvct_el0" : "=r" (tsc));
+   return tsc;
+ }
++#elif defined(__riscv)
++static uint64_t rdtsc()
++{
++  uint64_t tsc;
++  tsc = 0;
++  return tsc;
++}
+ #endif
+ 
+ CAMLprim CAMLweakdef uint64_t caml_rdtsc_unboxed(value unit) {